Networks, such as Local Area Networks (LANs), having a plurality of nodes (i.e., devices connected to the network) which communicate by transmitting packets, or frames, of information to other nodes on the network and by receiving packets of information from other nodes on the network are known. The transmitting node is referred to as the source node and the receiving node is referred to as the destination node. The packets generally include a header, data, and a trailer. The header includes an address portion identifying the source node (i.e., the source node address), and the destination node (i.e., the destination node address), and may include additional information, such as the type of data associated with the packet. The data provides the information to be communicated between the nodes, and the trailer includes error information, such as a CRC check.
Various types of networks are available, such as Ethernet version 2.0 LANs, Ethernet 802.3 LANs, and Fiber Distributed Data Interconnect (FDDI) LANs. It is often advantageous to permit communication between nodes on different networks of the same or different type (i.e., internetworking). In the case of internetworking, the network to which the source node is attached is referred to as the source network and the network to which the destination node is attached is referred to as the destination network.
Internetworking between networks of different types is complicated by the fact that the format of the header associated with each network type varies somewhat. For example, an Ethernet version 2.0 packet header includes the destination node address, the source node address, and a type field; whereas, an Ethernet 802.3 packet header includes the destination node address, the source node address, and a length field. An FDDI packet header includes, in addition to the source and destination node addresses, a frame control entry, a Logic Link Control (LLC) portion and may include a Sub-Network Access Protocol (SNAP) portion.
Internetworking devices, such as bridges and routers, for permitting communication between nodes on more than one network of the same or different type are known. Such devices generally include a plurality of Media Access Controllers (MACs), each one connected to a respective network for controlling the receipt and transmission of packets, a memory for storing a received packet prior to transmission to a destination network, a processor for providing any necessary packet manipulation, and control circuitry for governing packet storage, manipulation, and transmission. When interconnecting networks of different types, the device converts, or translates, the packet header format associated with the source network into the header format associated with the destination network. Packet header translation may require manipulation of the stored packet, such as by providing supplemental header information for transmission with the packet.
One technique for passing packets between different network types (i.e., translational internetworking) includes reading the entire received packet into a block of sequential buffer locations. The source node address identifies the source network and thus also the header format of the received packet and the destination node address identifies the destination network and thus the header format associated with the destination node. Based on a determination of the source node header format and the destination node header format, the processor determines whether and what type of header translation is necessary to transmit the received packet to the destination node. If supplemental header information is required to render the received packet header compatible with the format associated with the destination node, then a portion of the stored packet is read out of the buffer and written back into the buffer at another location, to permit the insertion of the supplemental header information at the appropriate sequential locations of the buffer. However, this technique disadvantageously requires many memory accesses to move a portion of the stored packet to a different location in the buffer and thus results in a concomitant increase in processing time.
Another translational internetworking technique similarly requires the entire received packet to be read into a block of sequential buffer locations and a determination to be made as to what, if any, translation is necessary to convert the received packet header into a format compatible with the destination node. However, rather than read out and write back a portion of the stored header as in the above described approach, this technique employs multiple pointers in the transmission of the stored packet. More particularly, if it is determined that the stored header requires supplemental header information for transmission to the destination node, then the supplemental header information is written into a block of buffer locations which are non-sequential with respect to the buffer locations in which the received packet is stored and pointers are provided to the start of the received header, the start of the supplemental header information and the start of the remainder of the packet, after the address header portion. These pointers are used by the control circuitry upon transmission of the packet to ensure that the supplemental header information is transmitted after the received header and before the received data. However, use of multiple pointers in this manner tends to increase processing time.
Some internetworking devices are used in conjunction with Dynamic Random Access Memory (DRAM) to provide buffers for storing received packets. Although DRAM tends to be relatively inexpensive, it suffers from the drawback that memory accesses are relatively slow, with typical access latencies on the order of one or more microseconds thereby aggravating the increase in processing time typically associated with conventional header translation techniques.
Static Random Access Memory (SRAM) is sometimes preferred to DRAM for use with internetworking devices due to the relatively faster memory access times, with latencies on the order of tens or hundreds of nanoseconds. However, a tradeoff must be made in terms of processing time and cost, since SRAM tends to be more expensive than DRAM per bit of storage.